This description relates to logic circuits.
FIG. 1 is a diagram of an example of an inverter 10 that includes a first p-type metal oxide semiconductor transistor (PMOS) 12 and a second PMOS transistor 14 that are connected in series between voltage VDD and ground. An output capacitor 16 is coupled to the first and second transistors 12 and 14. The inverter 10 has an input node IN for receiving an input voltage Vin and an output node OUT for providing an output voltage Vout.
FIG. 2 is a diagram of an equivalent circuit 20 of the inverter 10 when the input voltage Vin is at logic low. The transistors 12 and 14 are represented by operating impedances R1 22 and R2 24, respectively. The series-connected impedances R1 and R2 form a voltage divider.
FIG. 3 are graphs of signal waveforms 30 and 32 that represent an input voltage Vin and an output voltage Vout, respectively, of the inverter 10. When the input voltage Vin is at logic low, the output voltage Vout is equal to VDD*R2/(R1+R2). When the input voltage Vin is at logic high, the output voltage Vout is equal to Vth, in which Vth is the threshold voltage of the second transistor 14.
FIG. 4 is a diagram of an example of an inverter 40 that includes a first PMOS transistor 12, a second PMOS transistor 15, an output capacitor 16, a third PMOS transistor 42, and a coupling capacitor 44. The inverter 40 has an input node 46 for receiving an input voltage Vin and an output node 48 for providing an output voltage Vout.
FIG. 5 is a diagram of an equivalent circuit 50 of the inverter 40 when the input voltage Vin is at logic low. In this case, the inverter 40 functions similar to a voltage divider that includes resistors R1 and R2, similar to those shown in FIG. 2. The output voltage Vout is equal to VDD*R2/(R1+R2). The voltage at a first end 52 (see FIG. 4) of the coupling capacitor 44 is equal to VDD*R2/(R1+R2), and the voltage Vx at a second end 54 of the coupling capacitor 44 is equal to Vth.
FIG. 6 is a diagram of an equivalent circuit 60 of the inverter 40 when the input voltage Vin is at logic high. In this case, the first transistor 12 is turned off (hence not shown in the figure), the second transistor 15 remains on, and the voltage at the first end 52 of the coupling capacitor 44 decreases to Vth. Because the voltage difference between the first and second ends 52 and 54 of the coupling capacitor 44 is maintained at [VDD*R2/(R1+R2)−Vth], the voltage Vx at the second end 54 of the coupling capacitor 44 drops to [Vth−VDD*R2/(R1+R2)]. The output voltage Vout drops to VSS.
FIG. 7 shows graphs of signal waveforms 62, 64, and 66 that represent the input voltage Vin, output voltage Vout, and the voltage Vx, respectively.
Other logic circuits, such as NAND and NOR circuits, can also be constructed using a single type transistor. FIG. 8 is a diagram of an NAND logic circuit 70 constructed using PMOS transistors, including a first PMOS transistor 72, a second PMOS transistor 74, a third PMOS transistor 14, and an output capacitor 16. Input nodes 76 and 78 (which receive input signals Vin1 and Vin2, respectively) are connected to the gates of the transistors 72 and 74, respectively. An output node 80 (having an output signal Vout) is connected to the source of the transistor 74, drain of the transistor 14, and one end of the capacitor 16.
FIG. 9 shows graphs of signal waveforms 82, 84, and 86 of the input voltage Vin1, input voltage Vin2, and the output voltage Vout, respectively, of the NAND logic circuit 70.